Typically, a one-bit full adder circuit produces sum and carry output signals in response to two operand input signals and their complements, and a carry input signal and its complement.
Table 1, shown below, is a truth table for a typical one-bit full adder. In table 1 the operand input signals are designated X and Y, and the complements of the operand input signals are designated X and Y, respectively. The carry input signal is designated Z.sub.in, and the complement of the carry input signal is designated Z.sub.in. Similarly, the sum output signal is designated S and its complement is designated S, and the carry output signal is designated Z.sub.out and its complement is designated Z.sub.out.
TABLE 1 ______________________________________ Inputs Outputs X Y --X --Y Z.sub.in --Z.sub.in S --S Z.sub.out --Z.sub.out ______________________________________ 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 ______________________________________
When arithmetic operations on multidigit numbers are to be performed substantially simultaneously for all orders, a number of one-bit full adder circuits, equal to the number of digits, are connected in parallel. In this case, the carry output signal and/or its complement depending on the particular circuit arrangement, from a one-bit full adder circuit operably connected to add two same order digits becomes the carry input signal to the adjacent one-bit full adder circuit which is operably connected to add the two next higher order digits. (See H. Taub et al, "Digital Integrated Electrons", McGraw-Hill, Inc., 1977, pp. 362-363.) Consequently, the carry output signal at the most signficant bit is delayed by the propagation delay time of the carry signal through each one-bit full adder multiplied by the number of one-bit full adders. As a result of this, the time required for arithmetic operations is prolonged.
The propagation delay time of the carry signal is the time interval between the entry of a valid carry input signal into the one-bit full adder and the emergence of a valid carry output signal from the one-bit full adder. This time is dependent upon the number of transistor gates in the carry path between the carry input and the carry output. Accordingly, efforts have been directed to the development of one-bit full adder circuits comprising a minimum number of transistor gates and especially a minimum number of transistor gates in the carry path to reduce the carry delay.